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* 
* Copyright (c) 2008 Freescale Semiconductor;
* All Rights Reserved
*
* Copyright (c) 2004-2008 Embedded Access Inc.;
* All Rights Reserved
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* All Rights Reserved
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  
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**************************************************************************
*
* $FileName: timer_mpc83xx.c$
* $Version : 3.8.1.0$
* $Date    : May-12-2011$
*
* Comments:
*
*   This file contains timer functions for use with all supported mpc83xx CPUs
*   Verified on MPC8313rdb, MPC8349mITXe and MPC8377rdb
*   Derived from original 8349 BSP so names may not have all converted
*
*
*END************************************************************************/

#include "mqx_inc.h"
#include "bsp.h"


/*FUNCTION*-----------------------------------------------------------------
*
* Function Name   : _mpc83xx_timer_init_int_ticks
* Returned Value  : Timer Hardware Reference Value
* Comments        :
*   this function will set up MPC83xx PIT(Periodic Interval Timer)
*   to interrupt the processor on every system tick
*   (default: 5 ms or 200 ticks per second)
*
*END*---------------------------------------------------------------------*/

uint_32 _mpc83xx_timer_init_int_ticks
   ( 
      /* [IN] the tick rate wanted in ticks per second */
      uint_32            resolution,
      
      /* [IN] the processor external clock speed */
      /* Pass External clock speed if PIT is connected to 
         external clock and if you wish PIT to use external clock,
         else pass '0' */
      uint_32            external_clock
   )
{ /* Body */
   KERNEL_DATA_STRUCT_PTR       kernel_data;
   PSP_SUPPORT_STRUCT_PTR       support_ptr;
   MPC83xx_PIT_STRUCT_PTR       pit_ptr;
   uint_32                      immr;
   uint_32                      reference, clk;
   
   immr = (uint_32)BSP_IMMR_BASE;
   _GET_KERNEL_DATA(kernel_data);
   
   support_ptr = kernel_data->PSP_SUPPORT_PTR;
   
   pit_ptr = (MPC83xx_PIT_STRUCT_PTR)(immr + MPC83xx_PIT_BASE);
   
   /* Disable PIT interrupt at IPIC level */
   _mpc83xx_disable_interrupt(MPC83xx_PIT_VECTOR);
   
   /* Disable PIT */
   pit_ptr->PTCNR = 0;
   
   /* Clear event Register */
   pit_ptr->PTEVR = 0;
   
   /* Set input clock */
   if(external_clock) {
      /* Use External Clock as input clock */
   	  clk = external_clock;
      pit_ptr->PTCNR = MPC83xx_PIT_PTCNR_CLKIN_EXTERNAL;
   }
   else {
   	  /* Use CSB Clock as input clock */
   	  clk = support_ptr->CSBCLK;
   }
   /* Set Prescaler value */
   // PIT has 32bit counter and can count upto 4GHz, which is well above
   // the maximum processor supported clock rates. So no need to work out
   // prescaler, just set it to 1. 
   // In future if processor and PIT supports input clocks more than 4GHz,
   // then we need to modify this, till then let us save few execution cycles
   
   pit_ptr->PTPSR = 0;
   
   /* Set PIT reference value */
   reference = clk / resolution;
   pit_ptr->PTLDR = reference;

   /* Enable clock and Interrupt */
   pit_ptr->PTCNR |= (MPC83xx_PIT_PTCNR_CLK_ENABLE |
                      MPC83xx_PIT_PTCNR_INT_ENABLE);   
                      
   /* Enable Timer Interrupt at IPIC level  */
   _mpc83xx_enable_interrupt(BSP_TIMER_INTERRUPT_VECTOR);

   return(reference);
   
} /* Endbody */


/* EOF */
